1. Technical Field
The present invention relates to programmable logic devices, and more particularly to a method for checking memory cell state in a programmable logic device.
2. Description of the Prior Art
Referring to FIG. 1, prior art programmable logic devices (PLDs) typically use one or more interconnect arrays 10 that are selectively programmed via an array of memory cells 12 (e.g. an EPROM, an EEPROM, a flash EPROM, or a flash EEPROM) to provide various interconnections within the PLD that are specific to a desired design. In interconnect array 10, the control gate of a memory cell 12 is connected to one column of the memory array (referred to as a wordline 14), typically driven by an input signal to array 10; the drain of memory cell 12 is connected to one row of the memory array (referred to as a bitline 16), typically a common output of signal array 10; and the source of memory cell 12 is tied to ground or virtual ground.
An erased memory cell which has a low threshold voltage Vt is turned on by a standard voltage source Vcc, thereby pulling down the voltage on bitline 16. Thus, an erased memory cell 12 constitutes a connection in the array. In contrast, a programmed memory cell which has a threshold voltage Vt above voltage source Vcc is not capable of affecting the state of its bitline. Thus, a programmed memory cell 12 does not constitute an array connection. Typically, a sense amplifier 18 is provided to sense and amplify the voltage of a bitline 16, which may only vary by tens of millivolts, to ensure full logic levels on the output lines of array 10.
Before a PLD is programmed with a new user design, the PLD is completely erased (i.e. all memory cells within the device are placed in an erased state). The PLD may be erased by exposing it to ultra-violet light (e.g. standard UV EPROMs), or may be erased electrically (e.g flash EPROMs and EEPROMs). With either method, a check is required to ensure that the erase cycle was successful in completely erasing the PLD.
PLDs may be programmed out-of-system, i.e. before the PLDs are installed into an electronic assembly. For PLDs that are programmed out-of-system in a programming socket, much of the burden of determining if the PLD is erased is placed on the software program that controls the programming of the PLD. Currently, there is a trend to program and erase the PLDs in-system, i.e. after installation into an electronic assembly. Such in-system programming and erasing places more of the burden for performing the erase check (also referred to as a blank check) procedure on the PLD itself because the software program that controls the programming of the PLD has only restricted access to the PLD once the PLD is installed in-system.
When PLDs are programmed out-of-system in a programming socket, the normal READ or VERIFY mode of the PLD is typically used to perform a blank check on the device. Thus, the programming software provides a row and column address to the address pins of the PLD which in turn corresponds to one or more locations in the PLD memory array. The state of each addressed memory cell is then read out on the PLD's data pins. The programming software generates addresses for every row/column location in the PLD memory array and verifies that the memory cell at each such location is in an erased or blank state. This procedure is performed entirely by the programming software and is thus transparent to the user.
In-system programming and erase schemes typically limit the programming software to serial access to the PLD through a small number of the PLD's I/O pins, e.g. four or five pins. Because such serial access is slow, blank check schemes that require the software to generate all of the row/column memory addresses to verify that the PLD is entirely erased are less desirable. Thus, it is more desirable for the PLD to blank check itself without assistance from the programming software.
One known method of performing an in-system self-test is for the PLD to mimic those signals that the programming software would typically provide at the address pins of the device. Implementing this scheme requires providing on-chip address counters and control logic that is adapted to generate each individual row/column address for the PLD memory array and verify a blank result for each address location, thereby significantly increasing the amount of logic required to perform the blank check. Thus, this self test undesirably produces a larger, more complex device. Furthermore, for addressing schemes that are not necessarily sequential in nature, implementation of a self check scheme becomes even more complex because, while a sequential counter is easy to design, a counter that skips addresses requires more logic to indicate which addresses to skip. Accordingly, this approach is sometimes slower than a software driven blank check, and also produces a more complex PLD that has a larger die size.
Therefore, a need arises for a blank self test scheme for a PLD that does not rely upon external factors, such as programming software, and that does not burden the PLD with excessive circuitry.